Where to Read What — Series Map

1. Grace Blackwell → Vera Rubin: Platform Framing

Vera Rubin (VR NVL72) is the second generation of Nvidia's rack-scale Oberon architecture, succeeding Grace Blackwell (GB200 / GB300 NVL72).

• "Rack-scale" means a single 19-inch server rack — typically housing 72 GPUs in this case — is designed to operate as one large accelerator rather than as a stack of independent servers.
• Vera Rubin extends this thesis under the banner of "extreme co-design": (1) the silicon (the chips themselves), (2) the package (the metal+ceramic structure that holds and cools each chip), (3) the cold plate (the metal block circulating liquid coolant over each chip), (4) the compute tray (the chassis holding several chips at once), (5) the rack (the cabinet holding the trays), (6) and the cooling loop (the plumbing distributing coolant across the rack) are all designed together. At Rubin's power density, no single layer can move without forcing every other layer to change.

The competitive backdrop drives the engineering choices. AMD's MI450X Helios racks, AWS's Trainium 3 Gen2 UltraServer, and Google's TPU pods are all closing the gap on rack-scale AI infrastructure. Nvidia's response is to push every silicon component to the edge of what suppliers can build, and to tie them together more tightly through system-level design.

Each Rubin platform refresh covers six silicon products — Rubin GPU, Vera CPU, NVLink 6 Switch, ConnectX-9 (network interface card), BlueField-4 (data-processing unit that offloads networking and security), and Spectrum-6 (Ethernet switch for connecting racks). This note focuses on the engineering deltas from Blackwell.

2. Headline Specs: Rubin vs Blackwell at a Glance

A quick primer on the number formats referenced below: FP16, FP8, FP4 refer to floating-point numbers using 16, 8, or 4 bits respectively.

• Fewer bits means lower numerical precision but much faster arithmetic and far less memory traffic, so AI workloads have been steadily moving to narrower formats as researchers learn how to maintain model accuracy at lower precisions.
• PFLOPS = peta floating-point operations per second (10^15 operations/sec).
• TFLOPS = tera operations/sec (10^12).
• TB/s = terabytes per second of data movement.

FP throughput. Rubin's dense FP4 and FP8 FLOPs increase roughly ~3.5× versus GB200, while FP16 rises a more modest ~1.6×. Nvidia is allocating new silicon area to FP8 and FP4 because production training and inference workloads are migrating onto those formats. Nvidia brands its micro-scaled FP4 format as NVFP4. "Micro-scaled" means each small group of FP4 numbers shares a scaling factor, which preserves accuracy at low precision better than a global scaling factor would.

Memory. HBM capacity stays flat versus GB300 at 288 GB, while HBM bandwidth scales ~2.75–2.8× (from Blackwell's 8 TB/s using HBM3E to Rubin's 22 TB/s using HBM4). The architecture prioritizes bandwidth and low-precision compute over raw memory size.

Transistors. Full-chip transistor count rises from 208 B (Blackwell) to 336 B (Rubin), a ~60% increase. The new transistors come from bigger logic dies, the new I/O chiplets, and doubled FP4/FP8 Tensor Cores.

Where to Read What — Series Map